Nonvolatile semiconductor memory device and method for testing the same

ABSTRACT

A nonvolatile semiconductor memory device and a method for testing the same by which the faulty memory device causing the unexpected data rewrite can be surely excluded.  
     The test is carried out to judge whether or not a memory element storing a binary information corresponding to presence or not of an electric charge injected into a floating gate  13   a  arranged on a semiconductor substrate so as to be electrically isolated therefrom, the semiconductor substrate including a source S and a drain D formed thereon, can exactly hold the electric charge injected to the floating gate in advance. In the test, an approximately equal voltage is applied to the source and drain as the voltage for drawing out the electric charge held in the floating gate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a nonvolatile semiconductormemory device and a method for testing the same, and more particularlyto a nonvolatile semiconductor memory device like an erasable andprogrammable read-only memory (referred to as ‘EPROM’ hereinafter), theinformation written to which can be erased by irradiation of ultravioletrays, or an electrically erasable and programmable read-only memory(referred to as ‘EEPROM’ hereinafter), the information written to whichcan be electrically erased, and to a method for testing the EPROM orEEPROM.

[0003] 2. Related Art

[0004] In the nonvolatile semiconductor memory device of the type asdescribed above, there are used a lot of memory elements arranged as amatrix, of which each is provided with a floating gate and a controlgate as well. The memory elements of this kind vary their thresholdvalues depending on the presence or not of the electric charge injectedinto their floating gate.

[0005] For instance, in the memory element of the n-channel conductivetype, the threshold value of the memory element can be made higher byinjecting an electron into its floating gate, comparing with that of thememory element to which no electron injection is done. Accordingly, theinformation respectively stored in the electron injected memory elementand the no electron injected memory element can be made out based on thedifference between threshold values of these memory elements. Forinstance, when applying a predetermined gate voltage to theabove-mentioned control gate, the data ‘0’ can be read out from theelectron injected memory element while the data ‘1’ can be read out fromthe no electron injected memory element.

[0006] However, it would not be always guaranteed that the electriccharge once injected into the floating gate of the memory element stablyrests therein and the data ‘1’ or ‘0’ never fails to be read outcorrectly as described above. It might happen that the electric chargeinjected into the floating gate of the memory element is unexpectedlydischarged for some unknown reason. In this case, the whole data areobliged to be rewritten. In order to prevent such an unexpectedsituation as described above, all the nonvolatile semiconductor memorydevices newly coming from the production line are tested to examine ifthe electric charge injected into the floating gate is discharged or notunder the predetermined load condition.

[0007] In order to carry out the prior art test of this kind, theelectric charge is first injected in advance into the floating gate ofall the memory elements. Then, a predetermined voltages are appliedrespectively to the source, drain and control gate of each electriccharge injected memory element, for instance, 4.5V being applied to thedrain by making use of the regulator incorporated into the nonvolatilesemiconductor memory device, 3V to the source by making use of the writevoltage for data latch, and 0V to the control gate.

[0008] If the electric charge once injected into the floating gate ofthe memory element is discharged by applying the above-mentionedvoltages to the source, drain and control gate of the memory element,the memory element is judged to be a faulty product, and the nonvolatilesemiconductor memory device including this faulty memory element is alsojudged to be a faulty product and is sorted out from normal products.

[0009] As described above, in the prior art test method, only a voltagelower than that of the drain was applied to the source of each memoryelement by making use of the write voltage from the data latch, so thatthis test method has not always satisfied the demand for the more severeand reliable test for sorting the faulty product. Accordingly, it hasbeen desired to test the memory element under such a severer conditionthat the higher load is applied thereto, for instance.

SUMMARY OF THE INVENTION

[0010] Accordingly, an object of the invention is to provide a sortingtest method capable of much more severely sorting out the faulty memoryelement than the prior art test method. Another object of the inventionis to provide a nonvolatile semiconductor memory device capable of beingtested by means of the more severer sorting test method than the priorart one.

[0011] In order to achieve the objects as described above, the inventionadopts the following constitution.

[0012] Basically, the invention is characterized in that, in the testfor judging whether or not a memory elements storing a binaryinformation corresponding to the presence or not of an electric chargeinjected into a floating gate arranged on a semiconductor substrate soas to be electrically isolated therefrom, said semiconductor substrateincluding a source and a drain formed thereon, can exactly hold theelectric charge injected to the floating gate in advance, anapproximately equal voltage is applied to the source and drain as thevoltage for drawing out the electric charge held in the floating gate.

[0013] According to the invention, an approximately equal voltage isapplied to the source and drain as a voltage for drawing out theelectric charge injected into the floating gate in advance.

[0014] Furthermore, the nonvolatile semiconductor memory deviceaccording to the invention includes a power source unit, which makes iteasier to carry out the test method according to the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Certain preferred embodiments of the invention will now bedescribed in detail by way of examples and with reference to theaccompanying drawings, wherein constituents of the invention havingsubstantially like function and structure in each of the several figuresare identified by the like reference numeral or character in order toavoid the repetitive and redundant description thereabout, and wherein:

[0016]FIG. 1 is a circuit diagram showing the outline of a nonvolatilesemiconductor memory device according to the first embodiment of theinvention.

[0017]FIG. 2 is a circuit diagram showing the outline of a nonvolatilesemiconductor memory device according to the second embodiment of theinvention.

[0018]FIG. 3 is a circuit diagram showing the outline of a nonvolatilesemiconductor memory device according to the third embodiment of theinvention.

[0019]FIG. 4 is a circuit diagram showing the outline of a nonvolatilesemiconductor memory device according to the fourth embodiment of theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

[0020]FIG. 1 is a circuit diagram showing the outline of a nonvolatilesemiconductor memory device according to the first embodiment of theinvention. This embodiment will be described by way of an EPROM as anexample of the above-mentioned nonvolatile semiconductor memory device,the information written to which can be erased in a lump by irradiatingit with ultraviolet rays.

[0021] As shown in FIG. 1, the nonvolatile semiconductor memory device10 according to the present embodiment includes a plurality of wordlines 11 arranged in parallel with each other, a plurality of bit lines12 arranged such that they intersect the above word lines 11 at rightangles, and a plurality of memory elements 13 arranged corresponding toevery intersection point made by the above word and bit lines 11 and 12.

[0022] Furthermore, the nonvolatile semiconductor memory device 10includes a plurality of selection lines 14 running between adjacent wordlines 11 so as to be in parallel therewith, a plurality of selectiontransistors 15 made up of MOS transistors, a sense amplifier 16 fordetecting the electric potential of the bit line 12, a data latch 17 forholding the data write potential to each bit line 12, an output buffer18, a data I/O circuit 19, an input buffer 20, a control circuit 21, anaddress buffer 22, a row decoder 23, and a column decoder 24.

[0023] Still further, the nonvolatile semiconductor memory device 10includes a regulator 25 generating a suitable voltage to be applied tothe source S and the drain D of each memory element 13, a test modecircuit 26 receiving a test signal notifying the start of the test modeoperation, a level shifter 27 converting the voltage of the test signalinputted to the test mode circuit 26, and a switching circuit 28connecting each bit line 12 with the output line 25 a of the regulator25 based on the output signal from the level shifter 27.

[0024] The memory element 13 used herein is of the well known typewherein there are provided a pair of a source S and a drain D both ofwhich are defined, for instance, as n-type impurity doped regions formedon a p-type semiconductor substrate (not shown), a floating gate 13 aarranged above the region between the source S and the drain D such thatit is electrically isolated from the semiconductor substrate, and acontrol gate G arranged still above the floating gate 13 a such that itis electrically isolated from this floating gate.

[0025] In the memory element 13, if such a positive gate voltage thatexceeds a predetermined threshold value viewing on the basis of thesource S, is applied to the control gate G, an n-type conductive channelis formed between the source S and the drain D. Accordingly, the memoryelement 13 is an n-type conductive memory element wherein the source Sand the drain D come in the conducting state with the help of the n-typeconductive channel formed therebetween. If the electric charge isinjected into the floating gate 13 a, the threshold value of theelectric charged injected memory element 13 is increased comparing withthat of the no charge injected one. In the memory element 13 in whichthe n-type conductive channel is formed, the electron is used as theelectric charge to be injected into the floating gate 13 a.

[0026] In the memory element 13, a predetermined gate voltage is given,as a data read voltage, between the source S and the control gate G ofthe memory element 13, as described later.

[0027] In the memory element 13 in which no electron is injected intothe floating gate 13 a, the threshold value becomes relatively lowerthan the gate voltage at the time of the data read operation, so thatthe n-type conductive channel is formed between the source S and thedrain D with the above readout voltage. This corresponds to theinformation ‘1,’ for instance. Contrary to this, in the memory element13 in which the electron is injected into its floating gate 13 a, thethreshold value becomes relatively higher than the gate voltage at thetime of the data read operation, so that no channel is formed betweenthe source S and the drain D with the above readout voltage. Thiscorresponds to the information ‘0.’

[0028] Accordingly, the presence or not of the electric charge in thefloating gate 13 a of each memory element 13 corresponds to theinformation ‘0’ or ‘1.’

[0029] Again referring to FIG. 1, the source S of each memory element 13is connected with the bit line 12 of the corresponding column, and thedrain D of each memory element 13 is connected with the selection line14 extending between the adjacent word lines 11 to be in paralleltherewith. Furthermore, the control gate G of each memory element 13 isconnected with the word line 11 of the corresponding row.

[0030] Furthermore, each bit line 12 is connected, via each selectiontransistor 15 made up of a MOS transistor, with the sense amplifier 16detecting the electric potential of the bit line 12 and also with thedata latch 17 holding the data write electric potential for writing thedata to each bit line 12. The sense amplifier 16 is connected with thedata I/O circuit 19 via the output buffer 18, and the data latch 17 isconnected with the data I/O circuit 19 via the input buffer 20.

[0031] In the nonvolatile memory device 10, a control signal is inputtedto the control circuit 21 to select any one from among availableoperational modes, that is, the data write mode, the data readout mode,and the test mode.

[0032] Also, an address signal is inputted to the address buffer 22 inorder to select the address of the memory element 13 to which theselected operational mode is applied.

[0033] The address buffer 22 outputs a word line selection signal to therow decoder 23, in order to select the word line 11 corresponding to thememory element 13 selected according to the address signal, and alsooutputs the bit line selection signal to the column decoder 24, in orderto select the bit line 12 corresponding to the above memory element 13.

[0034] The row decoder 23 selects the word line 11 corresponding to thememory element 13 selected according to the word line selection signal.

[0035] The column decoder 24 puts the corresponding selection transistor15 in the conducting state, in order to connect the bit line 12corresponding to the above selected memory element 13 with the senseamplifier 16 and the data latch 17 as well according to the bit lineselection signal.

[0036] The regulator 25 functions as a power source generating asuitable voltage to be applied to the source S and the drain D of eachmemory element 13 according to the selected available operational mode,that is, the data write mode, the data read mode, or the test mode.

[0037] The regulator 25 is able to generate several different voltagesaccording to the operational mode selected based on the control signalfrom the control circuit 21. For instance, it generates 4.5V in the datawrite mode operation and the test mode operation as well while itgenerates 1.5V in the data read mode operation. The voltage asrespectively generated is applied to the drain D of each memory element13 via the selection line 14 connected with the output line 25 a of theregulator 25.

[0038] Again referring to FIG. 1, the switching circuit 28 of the firstembodiment includes a plurality of switching elements 28 a, of whicheach is made up of the MOS transistor arranged on every bit line 12.While each switching element 28 is receiving the output signal from thelevel shifter 27 through the gate thereof, it continues to connect thecorresponding bit line 12 with the output line 25 a of the regulator 25.

[0039] Having received the above-mentioned test signal, the test modecircuit 26 transfers it respectively to the row decoder 23, the columndecoder 25, and the control circuit 21, thereby putting each MOStransistor as the switching element 28 a of the switching circuit 28 inthe conducting state.

[0040] In the data write mode operation of the nonvolatile semiconductormemory device 10, the control circuit 21 controls the data latch 17 andthe sense amplifier 16 as well such that the former is put in theactivated state while the latter is put in the inactivated state. Inthis write mode operation, the regulator 25 outputs the write voltage of4.5V to its output line 25 a.

[0041] At this time, the test signal is not inputted to the test modecircuit 26, so that each switching element 28 a of the switching circuit28 electrically isolates the output line 25 from the bit line 12, thusany voltage generated by the regulator 25 being not applied to the bitline 12.

[0042] In the data write operation to each memory element 13, the datainputted to the data I/O circuit 19 is held as the write voltage in theactivated data latch 17 through the input buffer 20.

[0043] When the data to be written is the information ‘1’, the voltageof 3.0V is held in the data latch 17, for instance. When the data to bewritten is the information ‘0’, the voltage of 0V is held in the datalatch 17, for instance.

[0044] Accordingly, in the data write mode operation, for instance, thevoltage of 8V from the row decoder 23 is applied to the control gate Gof the memory element 13 selected according to the above-mentionedaddress signal, the voltage of 4.5V from the regulator 25 is applied tothe drain D of the same, and the voltage 3.0V or 0V corresponding to thedata from the data latch 17 is applied to the source S of the same.

[0045] When the voltage of 0V is applied to the source S of the selectedmemory element 13, the drain voltage expressed as the difference voltage4.5V=4.5V−0V made by the voltages respectively applied to the drain Dand the source S of the selected memory element 13, acts on the memoryelement 13, so that the hot electron generated by this drain voltage isinjected into the floating gate 13 a.

[0046] On the other hand, when the voltage of 3.0V is applied to thesource S of the selected memory element 13, only the drain voltageexpressed as the difference voltage 1.5=4.5V−3.0V made by the voltagesrespectively applied to the drain D and the source S of the selectedmemory element 13, acts on the memory element 13, so that the hotelectron like the above can not be generated, thus no electron injectioninto the floating gate 13 a being caused.

[0047] As a result, according to the write information ‘0’ or ‘1’ heldin the data latch 17, the binary information corresponding to thepresence or not of the electron injected into the floating gate 13 a ofthe memory element 13, is written to this memory element 13.

[0048] The write cycle of the data to the memory element 13 is repeatedwith regard to all the memory elements 13 responding to the change ofthe address signal inputted to the address buffer 22. With this, thedata write to each memory element 13 is finished.

[0049] In the nonvolatile semiconductor memory device 10 made up ofEPROM's, the electron injected into the floating gate 13 a of eachmemory element 13 can be drawn out by making use of the optical energyof the ultra violet rays irradiating each memory element 13, thusenabling the information stored in the nonvolatile semiconductor device10 to be erased in a lump.

[0050] In the data read mode operation of the nonvolatile semiconductormemory device 10, the control circuit 21 controls the sense amplifier 16and the data latch 17 as well such that the former is put in theactivated state while the latter is put in the inactivated state. Inthis data read mode operation, the regulator 25 outputs the readoutvoltage of 1.5V to its output line 25 a.

[0051] At this time, the test signal is not inputted to the test modecircuit 26, so that similar to the write mode operation, each switchingelement 28 a of the switching circuit 28 puts the output line 25 and thebit line 12 in such a state they are electrically isolated from eachother, thus no voltage generated from the regulator 25 being applied tothe bit line 12.

[0052] In the data readout from the memory element 13, the electricpotential of 0.1V for instance is given by the activated sense amplifier16, to the bit line 12 selected according to the selection signal fromthe column decoder 24. On the other hand, the electric potential of 3.3Vfor instance is given to the word line 11 selected according to theselection signal from the row decoder 24.

[0053] Accordingly, as the voltages of 0.1V and 1.5V are applied to thesource S and the drain D of the selected memory element 13,respectively, the voltage of about 1.4V is applied to the drain of theselected memory element 13 as the drain voltage. On one hand, as thevoltage of 3.3V is applied to the control gate G, the voltage of theabout 3.2V is applied between the source S and the control gate G of theselected memory element 13 as the gate voltage.

[0054] At this time, if no electron is injected into the floating gate13 a of the selected memory element 13, this memory element shows thethreshold value lower than the above gate voltage, thereby the memoryelement 13 being put in the conducting state. Thus, the electric currentcomes to flow, through the selected memory element 13, to the bit line12 connected therewith.

[0055] On the other hand, if the electron is injected into the floatinggate 13 a of the selected memory element 13, this memory element showsthe threshold value higher than the above gate voltage, thereby thememory element 13 being not put in the conducting state but put in thenon-conducting state.

[0056] As a result, the presence or not of the current flowing from thesequentially selected memory element 13 to the bit line 12 connectedtherewith is detected by the sense amplifier 16, and then, the detectionresult with regard to the presence or not of this detection current isexternally outputted as a readout voltage from the nonvolatilesemiconductor memory device 10 through the output buffer 18 and the dataI/O circuit 19 connected therewith.

[0057] In the nonvolatile semiconductor memory device 10, the unexpecteddischarge of the electric charge injected into the floating gate 13 aresults in the unexpected data rewrite of the data. Therefore, beforethe actual use of the nonvolatile semiconductor memory device 10, it istested whether or not there is a possibility that the unexpected datarewrite as called ‘Bit Line Disturbance’ takes place.

[0058] In this test mode operation, the electron is first injected intoeach floating gate 13 a of all the memory elements 13, respectively.

[0059] Then, the test signal being inputted to the test mode circuit 26,the row decoder 23 having received this signal through the test modecircuit 26 puts all the word line 11 in the non-selection state, so thatall the word line 11 is held at the voltage of 0V.

[0060] Also, the column decoder 24 receiving the above test signalthrough the test mode circuit 26, it holds all the selection transistors15 in the non-selection state, that is, the non-conducting state.

[0061] On the other hand, the test mode circuit 26 receiving the abovetest signal, the level shifter 27 makes each switching element 28 a ofthe switching circuit 28 conductive. With this, each bit line 12corresponding to each switching element 28 a is connected with theoutput line 25 a of the regulator 25.

[0062] In the test mode operation, this regulator 25 then outputs thevoltage of for instance 4.5V to apply it to the drain D of each memoryelement 13.

[0063] As the result of this, in the test mode operation of thenonvolatile semiconductor memory device 10, the voltage of 0V is appliedto the control gate G of each memory element 13 while the voltage of4.5V is equally applied to the source S and the drain D of the same,respectively.

[0064] In the prior art test, the voltage lower than the drain voltage,for instance 3.0V, was applied to the source S of each memory element 13by making use of the write voltage from the data latch 17.

[0065] In contrast to this, in case of the nonvolatile semiconductormemory device 10 according to the first embodiment, the voltage of forinstance 4.5V as the output from the regulator 25 can be equally appliedto the source S and drain D, so that these source S and drain D canapply the approximately same strong draw-out force to the electron heldin the floating gate 13 a. Thus, this means that the test can beexecuted under the more severe condition, that is, under the conditionusing the higher load.

[0066] If it is found after executing the above test that no electronhas been drawn out from the floating gate 13 a of any memory element 13,in other words, if it is found that all the memory elements hold theinformation ‘0’ in the readout mode operation, the nonvolatilesemiconductor memory device 10 is judged to be an acceptable product.Contrary to this, even if only one memory element 13 holds theinformation ‘1’, the nonvolatile semiconductor memory device 10 isjudged to be a faulty product to be rejected.

[0067] As described above, in the test mode operation of the nonvolatilesemiconductor memory device 10 according to the first embodiment, itbecomes possible to apply the equal draw-out voltage for drawing out theelectric charge, to the source S and drain D of the memory element 13.With this, it becomes possible to more surely exclude the faulty productthat might cause unexpected data rewrite, thus the screening effect ofthe faulty product being enhanced.

Second Embodiment

[0068] Now, referring to FIG. 2 showing the second embodiment accordingto the invention, it will be understood from this figure that theswitching element 28 a forming the switching circuit 28 has the sameelement structure as the memory element 13.

[0069] In this example, there is no need for the electric charge to beinjected into the floating gate 13 a of each switching element 28.Instead, the voltage exceeding the threshold value of that switchingelement is applied to the control gate G of each switching element 28 afrom the level shifter 27.

[0070] Furthermore, instead of injecting the electric charge into thefloating gate 13 a of each switching element 28 a, there can be used theswitching elements 28 a, into the floating gate 13 a of which noelectric charge is injected.

[0071] As already described in connection with the first embodiment, theswitching circuit 28 has been formed as an peripheral circuit includinga plurality of MOS transistors i.e. switching elements 28 a. Accordingto the second embodiment, however, the switching circuit 28 is formed bymaking use of switching elements 28 a having the same structure as thememory element 13, which can be more miniaturized in comparison with theMOS transistor as used in the first embodiment. Accordingly, it ispossible to suppress that the nonvolatile semiconductor memory device 10becomes larger in the size thereof.

Third Embodiment

[0072] The first and second embodiments shown in FIGS. 1 and 2, havebeen described by way of the example in which each switching element 28a is provided in correspondence with each bit line 12. In the thirdembodiment shown in FIG. 3, a switching circuit 28 can be formed bymeans of a single switching element which is provided between each bitline 12 and the output line 25 a of the regulator 25 and executes theopen/shut operation in response to the test signal from the levelshifter 27.

[0073] The switching element shown in FIG. 3 is basically the sameswitching element as each switching element 28 a adopted by the firstembodiment and is able to be formed by means of the MOS transistorhaving the gate receiving the signal from the level shifter 27, thesource and the drain.

[0074] The source and drain of this switching element 28 are insertedbetween the output line 25 a of the regulator 25 and a collective line29 connected with all the bit lines 12, so that receiving the testsignal from the level shifter 27, the switching element 28 connects allthe bit lines 12 with the output line 25 a of the regulator 25 in alump.

[0075] In the third embodiment shown in FIG. 3, each selectiontransistor 15 is arranged between the switching element 28 and each bitline 12, so that in the test mode operation, the selection transistor 15is put in the conducting state according to the selection signal fromthe column decoder 24. Therefore, in the test mode operation, the senseamplifier 16 and the data latch 17, both of which are connected witheach bit line 12, respectively, are held in the inactivated state by thecontrol signal from the control circuit 21.

[0076] As described above, in the nonvolatile semiconductor memorydevice 10 according to the third embodiment, the switching circuit 28can be realized by means of the single switching element 28, so that thepackaging space of the nonvolatile semiconductor memory device 10 isadvantageously prevented from being enlarged uselessly.

Fourth Embodiment

[0077] Now, let us refer to FIG. 4 showing the fourth embodimentaccording to the invention. In this embodiment, there is not providedsuch a switching circuit 28 that is used in the first through thirdembodiments of the invention. Instead of the switching circuit 28, theremay be provided a circuit serving as follows. That is, in the test modeoperation, the circuit applies a predetermined voltage outputted to theoutput line 25 a of the regulator 25 to the drain D of each memoryelement 13 through each selection line 14, and at the same time, has thedata latch 17 held the voltage of the output line 25 a, and then appliesthe voltage of the output line 25 a to the source S of each memoryelement 13 through the data latch 17.

[0078] According to the fourth embodiment, in the test mode operation,it becomes possible to have the output voltage from the regulator 25acted on the source S and drain D of the memory element 13 by additionof the wiring extending from the regulator 25 to the data latch 17 andprogramming of the control circuit 21, so that there is no need toprovide the switching circuit 28 for connecting the bit line 12 with theoutput line 25 a of the regulator 25. Accordingly, the fourth embodimentis most advantageous with regard to the design of the nonvolatilesemiconductor memory device 10, especially the design relating to thespace for packaging various elements of the memory device.

[0079] In the explanation about the several embodiments according to theinvention, the regulator 25 has been used as a power source in the testmode operation. However, it is possible to use an internal power sourceother than the regulator 25 in order to realize the nonvolatilesemiconductor memory device according to the invention. Furthermore, inorder to execute the test method according to the invention, it ispossible to use the power source other than the regulator 25incorporated in the nonvolatile semiconductor memory device 10, or anexternal power source not incorporated in the nonvolatile semiconductormemory device 10.

[0080] In the above description, the value of each voltage applied tothe floating gate 13 a, the source S and the drain D of each memoryelement 13 is merely an example for the purpose of explaining theinvention. Therefore, various voltage values may be adopted takingaccount of the characteristic of the memory element 13 as far as thevoltages applied to the source S and the drain D, respectively, areapproximately equal to each other.

[0081] The invention has been described so far by way of the memoryelement having the n-type conductive channel formed by the electron.However, the invention is also applicable to the memory element havingthe p-type conductive channel formed by the hole.

[0082] The invention has been described so far by way of the EPROM asthe nonvolatile semiconductor memory device in which the data write iscarried out by making use of the hot electron. However, the invention isapplicable to the nonvolatile semiconductor memory device of the othertype and the method for testing thereof, for instance a so-calledOne-Time PROM (OTP) covered by a package having no quartz glass windowfor irradiation of ultra violet rays, an EEPROM of which the writteninformation can be electrically erased, and so forth.

[0083] Moreover, for example, the present may be applicable to thefollowing test method.

[0084] A method for testing a nonvolatile semiconductor memory devicefor judging whether or not a memory element can surely hold the electriccharge injected into the floating gate in advance, said memory elementstoring a binary information corresponding to whether or not an electriccharge has been injected into a floating gate arranged on asemiconductor substrate so as to be electrically isolated therefrom,said semiconductor substrate including a source and a drain formedthereon, wherein the test is carried out by applying an approximatelyequal voltage to the source and drain as a voltage for drawing out theelectric charge held by the floating gate.

[0085] The voltage of 4.5V may be applied to the source and drain as atest voltage.

[0086] While preferred embodiments of the nonvolatile semiconductormemory device and the method for testing the same according to theinvention have been discussed with reference to the accompanyingdrawings, the invention is not limited to these embodiments as shown inthe drawings and described in this specification. It will be apparent tothose skilled in the art that changes and modifications can be madewithout departing from the principle and spirit of the invention, thescope of which is defined in the appended claims, and it is understoodthat those changes and modifications also belong to the technical scopeof the invention.

What is claimed is:
 1. A nonvolatile semiconductor memory devicecomprising: a plurality of memory elements each of which stores a binaryinformation corresponding an electric charge injected into a floatinggate arranged on a semiconductor substrate so as to be electricallyisolated therefrom, said semiconductor substrate including a source anda drain formed thereon; and a power source unit applying anapproximately same voltage to said source and drain in a test modeoperation for judging whether the electric charge injected into saidfloating gate in advance can be surely held or not.
 2. A nonvolatilesemiconductor memory device as claimed in claim 1, wherein said memoryelement further includes a control gate arranged on said floating gateso as to be electrically isolated therefrom, and said memory elementshows electrical conduction of the n-type due to a channel by electronformed between said source and drain regions when applying a gatevoltage exceeding the threshold value to said control gate, and in saidtest mode operation, a positive voltage viewing on the basis of saidcontrol gate is applied to said source and drain.
 3. A nonvolatilesemiconductor memory device as claimed in claim 2, wherein in said testmode operation, the approximately same positive electric potential isapplied to said source and drain when said control gate is held at thevoltage of 0V.
 4. A nonvolatile semiconductor memory device as claimedin claim 1, wherein said memory element further includes a control gatearranged so as to be electrically isolated from said floating gate, andsaid memory element shows the electrical conduction of the p-type due toa channel by hole formed between said source and drain when applying agate voltage less than the threshold value to said control gate, and inthe test mode operation, a positive voltage viewing on the basis of saidcontrol gate is applied to said source and drain.
 5. A nonvolatilesemiconductor memory device as claimed in claim 4, wherein in said testmode operation, the equal positive electric potential is applied to saidsource and drain when said control gate is held at the voltage of 0V. 6.A nonvolatile semiconductor memory device as claimed in claim 1, whereinsaid power source unit includes a power source applying a predeterminedvoltage to said drain in the test mode operation, and a switchingelement inserted between said power source and the bit line connectedwith said source in order to apply a predetermined same voltage to saidsource and drain by using said power source as a common power source inthe test mode operation.
 7. A nonvolatile semiconductor memory device asclaimed in claim 6, wherein said power source is made up of a regulatorcapable of applying a predetermined voltage to said drain according tovarious operational modes, that is, the data read mode, the data writemode, and the test mode.
 8. A nonvolatile semiconductor memory device asclaimed in claim 7, wherein in the test mode operation, the voltage ofsaid regulator is applied to said source through a latch for temporarilyholding the data written to said memory element in the data write modeoperation.
 9. A nonvolatile semiconductor memory device as claimed inclaim 6, wherein there are provided a plurality of bit lines, each ofwhich includes said plurality of memory elements electrically connectedtherewith, and also includes said switching element electricallyconnected therewith.
 10. A nonvolatile semiconductor memory device asclaimed in claim 9, wherein said switching element is formed by makinguse of an element having the same structure as the element forming saidmemory element.
 11. A nonvolatile semiconductor memory device as claimedin claim 6, wherein there are provided a plurality of bit lines, each ofwhich includes said plurality of memory elements electrically connectedtherewith, and said plurality of bit lines can be connected with saidpower source via said single switching element.
 12. A nonvolatilesemiconductor memory device as claimed in claim 1, wherein said powersource unit applies the voltage of 4.5 equally to said source and drainin the test mode operation.
 13. A method for testing a nonvolatilesemiconductor memory device for judging whether or not a memory elementcan surely hold the electric charge injected into the floating gate inadvance, said memory element storing a binary information correspondingto whether or not an electric charge has been injected into a floatinggate arranged on a semiconductor substrate so as to be electricallyisolated therefrom, said semiconductor substrate including a source anda drain formed thereon, wherein the test is carried out by applying anapproximately equal voltage to the source and drain as a voltage fordrawing out the electric charge held by the floating gate.
 14. A methodfor testing a nonvolatile semiconductor memory device as claimed inclaim 13, wherein the voltage of 4.5V is applied to said source anddrain as a test voltage.
 13. A nonvolatile memory device comprising: aplurality of floating gate type memory cell transistors formed on asemiconductor substrate, each of the cell transistors has a source, adrain and a control gate; a plurality of word lines connected to thecontrol gates of the cell transistors; a plurality of bit linesconnected to the sources of the cell transistors; a select lineconnected to the drains of the cell transistors; a test mode circuit foroutputting a test mode signal; a regulator connected to the test modecircuit for providing a first voltage to the select line in response tothe test mode signal; and a switching circuit for connecting the selectline with the bit lines in response to the test mode signal.
 14. Anonvolatile memory devices as claimed in claim 13, further comprising anaddress circuit connected to the word lines and bit lines for selectingone of the word lines and one of the bit lines in response to an addresssignal.
 15. A nonvolatile memory device as claimed in claim 13, furthercomprising an input/output circuit for transferring data received fromone of the cell transistors and from an outside of the nonvolatilememory device.
 16. A nonvolatile memory device as claimed in claim 15,wherein the input/output circuit includes a sense amplifier, a datalatch circuit, an output buffer circuit and input buffer circuit.
 17. Anonvolatile memory device as claimed in claim 14, wherein the addresscircuit includes an address buffer receiving an address signal, a rowdecoder connected to the address buffer and the word lines and a columndecoder connected to the address buffer and the bit lines.
 18. Anonvolatile memory device as claimed in claim 13, further comprising acontrol circuit connected to the regulator for providing a controlsignal.
 19. A nonvolatile memory device as claimed in claim 13, whereinthe switching circuit includes a plurality of switching transistors eachof which is connected between the select line and one of the bit lines.20. A nonvolatile memory device as claimed in claim 19, wherein theswitching transistors are floating gate type transistors.
 21. Anonvolatile memory device as claimed in claim 15, further comprising aplurality of selecting transistors each of which is connected to theinput output circuit and one of the bit lines.
 22. A nonvolatile memorydevice as claimed in claim 21, wherein the switching circuit including aswitching transistor connected between the select line and the selectingtransistors.
 23. A nonvolatile memory device comprising: a plurality ofmemory cell transistors formed on a semiconductor substrate, each of thecell transistors has a source, a drain, a floating gate and a controlgate; a plurality of word lines connected to the control gates of thecell transistors; a plurality of bit lines connected to the sources ofthe cell transistors; a select line connected to the drains of the celltransistors; a regulator for providing a first voltage to the selectline when a test mode signal is received thereto; and a switchingcircuit for connecting the select line with the bit lines when the testmode signal is received thereto.
 24. A nonvolatile memory device asclaimed in claim 23, further comprising an address circuit connected tothe word lines and bit lines for selecting one of the word lines and oneof the bit lines in response to an address signal.
 25. A nonvolatilememory device as claimed in claim 24, wherein the address circuitincludes an address buffer receiving an address signal, a row decoderconnected to the address buffer and the word lines and a column decoderconnected to the address buffer and the bit lines.
 26. A nonvolatilememory device as claimed in claim 23, further comprising an input/outputcircuit for transferring data received from one of the cell transistorsand from an outside of the nonvolatile memory device.
 27. A nonvolatilememory device as claimed in claim 26, wherein the input/output circuitincludes a sense amplifier, a data latch circuit, an output buffercircuit and input buffer circuit.
 28. A nonvolatile memory device asclaimed in claim 23, wherein the switching circuit includes a pluralityof switching transistors each of which is connected between the selectline and one of the bit lines.
 29. A nonvolatile memory device asclaimed in claim 23, wherein the switching transistors are floating gatetype transistors.
 30. A nonvolatile memory device as claimed in claim26, further comprising a plurality of selecting transistors each ofwhich is connected to the input/output circuit and one of the bit lines.31. A nonvolatile memory device as claimed in claim 30, wherein theswitching circuit including a switching transistor connected between theselect line and the selecting transistors.